【【简单systyem verilog 语言学习使用二— 新adder加法器 】】
adder.v
module addernew ( input clk , input rst_n , input [ 2 : 0 ] in_a , input [ 2 : 0 ] in_b , input sel , output reg [ 4 : 0 ] sum , output reg [ 4 : 0 ] carry) ; always@( posedge clk or negedge rst_n ) beginif ( rst_n == 0 ) begincarry <= 0 ; sum <= 0 ; endelse beginif ( sel == 0 ) begin{ carry, sum } <= in_a + in_b ; endelse begin{ carry, sum } <= in_a * in_b ; endendendendmodule
adder_tb.sv
class input_0; static int count = 0 ; int id; logic [ 2 : 0 ] ina; int arr[ 5 ] = '{ 1 , 2 , 3 , 4 , 5 } ; function new ( ) ; this. id = count++ ; endfunctiontask showk ( ) ; foreach ( arr[ i] ) beginautomatic int k = arr[ i] ; $write ( "%d\n" , k) ; endendtaskfunction void run ( int a) ; ina = a; $display ( "ina number is %3d" , ina) ; endfunction
endclassmodule test ( ) ; input_0 inst_a, inst_b; logic clk; logic rst_n; logic sel; logic [ 2 : 0 ] in_a, in_b; logic [ 4 : 0 ] sum, carry; initial beginclk = 0 ; forever #5 clk = ~ clk; endaddernew uadder ( . clk ( clk) , . rst_n ( rst_n) , . in_a ( in_a) , . in_b ( in_b) , . sel ( sel) , . sum ( sum) , . carry ( carry) ) ; initial beginrst_n = 0 ; inst_a = new ( ) ; inst_b = new ( ) ; $display ( "inst_a id = %d" , inst_a. id) ; $display ( "inst_b id = %d" , inst_b. id) ; inst_a. showk ( ) ; inst_b. showk ( ) ; #10 rst_n = 1 ; sel = 1 ; inst_a. run ( 3 ) ; inst_b. run ( 2 ) ; in_a = inst_a. ina; in_b = inst_b. ina; #105 ; $display ( "ina = %3d, inb = %3d, sel = %d, sum = %5d, carry = %5d" , in_a, in_b, sel, sum, carry) ; $display ( "time = %t" , $time) ; end
endmodule