使用3-8译码器①实现逻辑函数
描述
下表是74HC138译码器的功能表.
E3 | E2_n | E1_n | A2 | A1 | A0 | Y0_n | Y1_n | Y2_n | Y3_n | Y4_n | Y5_n | Y6_n | Y7_n |
x | 1 | x | x | x | x | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
x | x | 1 | x | x | x | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
0 | x | x | x | x | x | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
②请使用3-8译码器①和必要的逻辑门实现函数
可在本题答案中添加并例化3-8译码器①代码,3-8译码器①代码如下:
module decoder_38(input E1_n ,input E2_n ,input E3 ,input A0 ,input A1 ,input A2 ,output wire Y0_n , output wire Y1_n , output wire Y2_n , output wire Y3_n , output wire Y4_n , output wire Y5_n , output wire Y6_n , output wire Y7_n
);
wire E ;
assign E = E3 & ~E2_n & ~E1_n;
assign Y0_n = ~(E & ~A2 & ~A1 & ~A0);
assign Y1_n = ~(E & ~A2 & ~A1 & A0);
assign Y2_n = ~(E & ~A2 & A1 & ~A0);
assign Y3_n = ~(E & ~A2 & A1 & A0);
assign Y4_n = ~(E & A2 & ~A1 & ~A0);
assign Y5_n = ~(E & A2 & ~A1 & A0);
assign Y6_n = ~(E & A2 & A1 & ~A0);
assign Y7_n = ~(E & A2 & A1 & A0);endmodule
输入描述:
input A ,
input B ,
input C
输出描述:
output wire L
解题思路:
与VL17中使用Verilog代码实现全减器的思路一致;
将逻辑函数化成输入变量的最小项之和(最小项表达式);
module decoder0(input A ,input B ,input C ,output wire L
);
wire [7:0] Y_t;
decoder_38 DE38 (.E1_n(1'b0) , .E2_n(1'b0), .E3(1'b1),.A0(C), .A1(B), .A2(A),.Y0_n(Y_t[0]), .Y1_n(Y_t[1]), .Y2_n(Y_t[2]), .Y3_n(Y_t[3]),.Y4_n(Y_t[4]), .Y5_n(Y_t[5]), .Y6_n(Y_t[6]), .Y7_n(Y_t[7]));assign L = ~Y_t[1] | ~Y_t[3] | ~Y_t[7] | ~Y_t[6];endmodule