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1、题目2、分析独热码只有1bit为1其它位全为03、代码module top_module ( input clk, input areset, input x, output z ); parameter A2b01,B2b10; reg [1:0]state,next_state; always(posedge clk,posedge areset)begin if(areset) stateA; else statenext_state; end always(*)begin case(state) A:begin next_statex?B:A;zx;end B:begin next_stateB;z~x;end default:begin next_stateA;z1b0;end endcase end endmodule4、结果 
长河君 · 2026/8/3 0:15:31 · 阅读 1.2k verilog HDLBits刷题[Finite State Machines]“Exams/ece241 2014 q5b”---Q5b:Serial two‘s complementer
1、题目2、分析独热码只有1bit为1其它位全为03、代码module top_module ( input clk, input areset, input x, output z ); parameter A2b01,B2b10; reg [1:0]state,next_state; always(posedge clk,posedge areset)begin if(areset) stateA; else statenext_state; end always(*)begin case(state) A:begin next_statex?B:A;zx;end B:begin next_stateB;z~x;end default:begin next_stateA;z1b0;end endcase end endmodule4、结果