精品专栏推荐：从零学会 CST 仿真全流程_一只豌豆象的博客-CSDN博客版权声明：本文为CSDN博主「一只豌豆象」的原创文章，收录于「信号完整性」技术专栏，并同步发布于知乎同名专栏，转载或引用请附上原文出处链接及本声明。目录摘要前言一、Differential clock timing差分系统时钟 CK 时序1.1 Average time for clock signal - tCK(avg)1.2 Average time for clock signal in high state - tCH(avg)1.3 Average time for clock signal in low state - tCL(avg)1.4 Absolute time for clock signal - tCK(abs)1.5 Absolute time for clock signal in high state - tCH(abs)1.6 Absolute time for clock signal in low state - tCL(abs)1.7 Periodic jitter for clock signal - tJIT(per)1.8 Cycle-to-cycle jitter for clock signal - tJIT(cc)二、Differential write clock timing 差分写时钟 WCK 时序2.1 Average write clock period - tWCK(avg)2.2 Average time for write clock signal in high state - tWCKH(avg)2.3 Average time for write clock signal in low state - tWCKL(avg)2.4 Absolute time for write clock signal - tWCK(abs)2.5 Absolute time for write clock signal in high state - tWCKH(abs)2.6 Absolute time for write clock signal in low state - tWCKL(abs)2.7 Periodic jitter for write clock signal - tJIT(per)_WCK2.8 Cycle-to-cycle jitter for write clock signal - tJIT(cc)_WCK2.9 Number of errors in write clock data - tERR(nper_WCK)三、WCKtoCK timing相位偏移四、Single-ended mode clock timingCK 单端模式时序4.1 Clock single-ended CK pulse at Vddq/2±VCKIVW/2 - tCKHL4.2 Clock single-ended CK positive pulse at Vddq/2 - tCKH4.3 Clock single-ended CK negative pulse at Vddq/2 - tCKL五、Single-ended mode write clock timingWCK 单端模式时序5.1 Write clock single-ended WCK pulse at Vddq/2±VCKIVW/2 - tWCKHL5.2 Write clock single-ended WCK positive pulse at Vddq/2 - tWCKH5.3 Clock single-ended WCK negative pulse at Vddq/2 - tWCKL小结摘要时钟质量直接决定 LPDDR5 系统能否稳定工作。本篇完整解读系统时钟 CK、写时钟 WCK 的全套时序指标：平均 / 绝对周期、高低电平脉冲宽度、周期性抖动 tJIT (per)、周期间抖动 tJIT (cc)、多周期累积误差 tERR、WCK‑CK 相位偏移`tWCK2CK`，以及单端模式 CK/WCK 脉冲时序；解释每个指标物理含义、统计窗口、计算公式，给出工程测试注意事项。前言LPDDR5 拥有两套差分时钟：系统时钟`CK_t/CK_c`，写时钟`WCK_t/WCK_c`。CK 用于命令地址采样；WCK 专门用于写 DQ 数据采样。两套时钟都需要测试周期、占空比、各类抖动，同时存在 WCK 相对于 CK 的相位对齐要求 WCK2CK leveling。很多测试失败来源于对抖动统计窗口、单端模式时