verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tff”---T flip-flop 1、题目2、分析先重置再切换为1的状态自由发挥吧答案不唯一3、代码module top_module (); reg clk; reg reset; reg t; wire q; initial begin clk 1b0; reset 1b0; t 1b0; #10 reset 1b1; #10 begin reset 1b0; t1b1;end end always #5 clk ~clk; tff tff_inst(clk,reset,t,q); endmodule 或者 module top_module (); reg clk; reg reset; reg t; wire q; initial begin clk 1b0; reset 1b0; t 1b1; #10 begin reset 1b1;t 1b0;end #10 begin reset 1b0; t1b1;end end always #5 clk ~clk; tff tff_inst(clk,reset,t,q); endmodule4、结果