AD9361，数据接口

CMOS

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LVDS

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Xilinx原语IBUFDS、OBUFDS

IBUFDS、和OBUFDS都是差分信号缓冲器，用于不同电平接口之间的缓冲和转换。IBUFDS 用于差分输入，OBUFDS用于差分输出。

IBUFDS

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https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/IBUFDS


//   IBUFDS    : In order to incorporate this function into the design,
//   Verilog   : the following instance declaration needs to be placed
//  instance   : in the body of the design code.  The instance name
// declaration : (IBUFDS_inst) and/or the port declarations within the
//    code     : parenthesis may be changed to properly reference and
//             : connect this function to the design.  All inputs
//             : and outputs must be connected.//  <-----Cut code below this line---->// IBUFDS: Differential Input Buffer//         Kintex-7// Xilinx HDL Language Template, version 2019.1IBUFDS #(.DIFF_TERM("FALSE"),       // Differential Termination.IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" .IOSTANDARD("DEFAULT")     // Specify the input I/O standard) IBUFDS_inst (.O(O),  // Buffer output.I(I),  // Diff_p buffer input (connect directly to top-level port).IB(IB) // Diff_n buffer input (connect directly to top-level port));// End of IBUFDS_inst instantiation

OBUFDS

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https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/OBUFDS

//     OBUFDS      : In order to incorporate this function into the design,
//     Verilog     : the following instance declaration needs to be placed
//    instance     : in the body of the design code.  The instance name
//   declaration   : (OBUFDS_inst) and/or the port declarations within the
//      code       : parenthesis may be changed to properly reference and
//                 : connect this function to the design.  Delete or comment
//                 : out inputs/outs that are not necessary.//  <-----Cut code below this line---->// OBUFDS: Differential Output Buffer//         Kintex-7// Xilinx HDL Language Template, version 2019.1OBUFDS #(.IOSTANDARD("DEFAULT"), // Specify the output I/O standard.SLEW("SLOW")           // Specify the output slew rate) OBUFDS_inst (.O(O),     // Diff_p output (connect directly to top-level port).OB(OB),   // Diff_n output (connect directly to top-level port).I(I)      // Buffer input);// End of OBUFDS_inst instantiation

拓展： IOBUFDS


//     IOBUFDS   : In order to incorporate this function into the design,
//     Verilog   : the following instance declaration needs to be placed
//    instance   : in the body of the design code.  The instance name
//   declaration : (IOBUFDS_inst) and/or the port declarations within the
//      code     : parenthesis may be changed to properly reference and
//               : connect this function to the design.  Delete or comment
//               : out inputs/outs that are not necessary.//  <-----Cut code below this line---->// IOBUFDS: Differential Bi-directional Buffer//          Kintex-7// Xilinx HDL Language Template, version 2019.1IOBUFDS #(.DIFF_TERM("FALSE"),     // Differential Termination ("TRUE"/"FALSE").IBUF_LOW_PWR("TRUE"),   // Low Power - "TRUE", High Performance = "FALSE" .IOSTANDARD("BLVDS_25"), // Specify the I/O standard.SLEW("SLOW")            // Specify the output slew rate) IOBUFDS_inst (.O(O),     // Buffer output.IO(IO),   // Diff_p inout (connect directly to top-level port).IOB(IOB), // Diff_n inout (connect directly to top-level port).I(I),     // Buffer input.T(T)      // 3-state enable input, high=input, low=output);// End of IOBUFDS_inst instantiation

Xilinx原语 BUFG,BUFIO,BUFR

BUFG

https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/BUFG

全局缓冲， BUFG 的输出到达 FPGA 内部的 IOB、 CLB、块 RAM 的时钟延迟和抖动最小.

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// BUFG: Global Clock Simple Buffer
//       7 Series
// Xilinx HDL Language Template, version 2024.1BUFG BUFG_inst (.O(O), // 1-bit output: Clock output.I(I)  // 1-bit input: Clock input
);// End of BUFG_inst instantiation

BUFIO

https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/BUFIO

BUFIO 是 IO 时钟网络，其独立于全局时钟资源，适合采集源同步数据。它只能驱动 IO Block里面的逻辑，不能驱动 CLB 里面的 LUT， REG 等逻辑。

BUFIO 在采集源同步 IO 数据时，提供非常小的延时。但是不能驱动FPGA的内部逻辑，需要BUFIO和BUFG搭配起来使用以实现最佳的性能。
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// BUFIO: Local Clock Buffer for I/O
//        7 Series
// Xilinx HDL Language Template, version 2024.1BUFIO BUFIO_inst (.O(O), // 1-bit output: Clock output (connect to I/O clock loads)..I(I)  // 1-bit input: Clock input (connect to an IBUF or BUFMR).
);// End of BUFIO_inst instantiation

BUFR

BUFR 是 regional 时钟网络，它的驱动范围只能局限在一个 clock region 的逻辑。 BUFR 相比 BUFG 的最大优势是偏斜和功耗都比较小。
https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/BUFR


// BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
//       7 Series
// Xilinx HDL Language Template, version 2024.1BUFR #(.BUFR_DIVIDE("BYPASS"),   // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8".SIM_DEVICE("7SERIES")  // Must be set to "7SERIES"
)
BUFR_inst (.O(O),     // 1-bit output: Clock output port.CE(CE),   // 1-bit input: Active high, clock enable (Divided modes only).CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only).I(I)      // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);// End of BUFR_inst instantiation

Xilinx原语 ISERDESE2,OSERDESE2

ISERDESE2

Primitive: Input SERial/DESerializer with Bitslip


// ISERDESE2: Input SERial/DESerializer with Bitslip
//            7 Series
// Xilinx HDL Language Template, version 2024.1ISERDESE2 #(.DATA_RATE("DDR"),           // DDR, SDR.DATA_WIDTH(4),              // Parallel data width (2-8,10,14).DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE).DYN_CLK_INV_EN("FALSE"),    // Enable DYNCLKINVSEL inversion (FALSE, TRUE)// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1).INIT_Q1(1'b0),.INIT_Q2(1'b0),.INIT_Q3(1'b0),.INIT_Q4(1'b0),.INTERFACE_TYPE("MEMORY"),   // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE.IOBDELAY("NONE"),           // NONE, BOTH, IBUF, IFD.NUM_CE(2),                  // Number of clock enables (1,2).OFB_USED("FALSE"),          // Select OFB path (FALSE, TRUE).SERDES_MODE("MASTER"),      // MASTER, SLAVE// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1).SRVAL_Q1(1'b0),.SRVAL_Q2(1'b0),.SRVAL_Q3(1'b0),.SRVAL_Q4(1'b0)
)
ISERDESE2_inst (.O(O),                       // 1-bit output: Combinatorial output// Q1 - Q8: 1-bit (each) output: Registered data outputs.Q1(Q1),.Q2(Q2),.Q3(Q3),.Q4(Q4),.Q5(Q5),.Q6(Q6),.Q7(Q7),.Q8(Q8),// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports.SHIFTOUT1(SHIFTOUT1),.SHIFTOUT2(SHIFTOUT2),.BITSLIP(BITSLIP),           // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to// CLKDIV when asserted (active High). Subsequently, the data seen on the Q1// to Q8 output ports will shift, as in a barrel-shifter operation, one// position every time Bitslip is invoked (DDR operation is different from// SDR).// CE1, CE2: 1-bit (each) input: Data register clock enable inputs.CE1(CE1),.CE2(CE2),.CLKDIVP(CLKDIVP),           // 1-bit input: TBD// Clocks: 1-bit (each) input: ISERDESE2 clock input ports.CLK(CLK),                   // 1-bit input: High-speed clock.CLKB(CLKB),                 // 1-bit input: High-speed secondary clock.CLKDIV(CLKDIV),             // 1-bit input: Divided clock.OCLK(OCLK),                 // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity.DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion.DYNCLKSEL(DYNCLKSEL),       // 1-bit input: Dynamic CLK/CLKB inversion// Input Data: 1-bit (each) input: ISERDESE2 data input ports.D(D),                       // 1-bit input: Data input.DDLY(DDLY),                 // 1-bit input: Serial data from IDELAYE2.OFB(OFB),                   // 1-bit input: Data feedback from OSERDESE2.OCLKB(OCLKB),               // 1-bit input: High speed negative edge output clock.RST(RST),                   // 1-bit input: Active high asynchronous reset// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports.SHIFTIN1(SHIFTIN1),.SHIFTIN2(SHIFTIN2)
);// End of ISERDESE2_inst instantiation

OSERDESE2

7系列FPGA器件中的专用并串转换器。

Primitive: Output SERial/DESerializer with bitslip


// OSERDESE2: Output SERial/DESerializer with bitslip
//            7 Series
// Xilinx HDL Language Template, version 2024.1OSERDESE2 #(.DATA_RATE_OQ("DDR"),   // DDR, SDR.DATA_RATE_TQ("DDR"),   // DDR, BUF, SDR.DATA_WIDTH(4),         // Parallel data width (2-8,10,14).INIT_OQ(1'b0),         // Initial value of OQ output (1'b0,1'b1).INIT_TQ(1'b0),         // Initial value of TQ output (1'b0,1'b1).SERDES_MODE("MASTER"), // MASTER, SLAVE.SRVAL_OQ(1'b0),        // OQ output value when SR is used (1'b0,1'b1).SRVAL_TQ(1'b0),        // TQ output value when SR is used (1'b0,1'b1).TBYTE_CTL("FALSE"),    // Enable tristate byte operation (FALSE, TRUE).TBYTE_SRC("FALSE"),    // Tristate byte source (FALSE, TRUE).TRISTATE_WIDTH(4)      // 3-state converter width (1,4)
)
OSERDESE2_inst (.OFB(OFB),             // 1-bit output: Feedback path for data.OQ(OQ),               // 1-bit output: Data path output// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each).SHIFTOUT1(SHIFTOUT1),.SHIFTOUT2(SHIFTOUT2),.TBYTEOUT(TBYTEOUT),   // 1-bit output: Byte group tristate.TFB(TFB),             // 1-bit output: 3-state control.TQ(TQ),               // 1-bit output: 3-state control.CLK(CLK),             // 1-bit input: High speed clock.CLKDIV(CLKDIV),       // 1-bit input: Divided clock// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each).D1(D1),.D2(D2),.D3(D3),.D4(D4),.D5(D5),.D6(D6),.D7(D7),.D8(D8),.OCE(OCE),             // 1-bit input: Output data clock enable.RST(RST),             // 1-bit input: Reset// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each).SHIFTIN1(SHIFTIN1),.SHIFTIN2(SHIFTIN2),// T1 - T4: 1-bit (each) input: Parallel 3-state inputs.T1(T1),.T2(T2),.T3(T3),.T4(T4),.TBYTEIN(TBYTEIN),     // 1-bit input: Byte group tristate.TCE(TCE)              // 1-bit input: 3-state clock enable
);// End of OSERDESE2_inst instantiation