xmos 相关知识--- xn文件解析

1.XN 文件解析

type 声明是device

name 是名称

tile 资源声明一个是XCore 一个是 usb 相关的物理层资源

package 对应芯片，包含两个Node 和一个link

两个node ，一个是xcore 一个是USB，每个node 都有一个id号，从0开始

xrun: Cannot load image, XCore 0 is not enabled 不能刷写可能原因

1) Check the status of the RST_N pin on the CPU. What is the logic level after boot? It should be HIGH to allow for the CPU and JTAG interface to run.

2) Check the clock (24M) at the CPU. Must be running to allow for CPU and JTAG operation. The crystal loading caps used on your design match the XMOS ref design but should be tweaked varying with the crystal manufacturer's recommendation. Often the loading caps vary with the vendor of the crystal. If the clock runs upon every power up cycle, then not a problem. Other thoughts are to source a fixed 3v3 crystal oscillator in a single device and just use it for the 24M clock source. This is 100% guaranteed to power up and run (be sure that OE pin on the oscillator = "1" to enable).

3) Check the voltage rails of each power rail.

4) Was this custom PCB, hand built or automated build? Reflow with a hot air tool the XMOS CPU to be sure the ground (paddle) bottom is soldered. This can raise the same error if the ground paddle is not soldered. This is a common root cause of this error on past reviews. Even better if you can get the XRAY view of the CPU to double check the same soldering details.

Cannot load image, XCore 0 is not enabled

This error message means that the XTAG or XTAG2 JTAG debug adapter can access the JTAG tap on the device, but cannot access the XCore tap on the device.

Possible reasons for this occurring can include:

1. The JTAG interface to the XCore has been disabled in the OTP security register.

2. The device is being permanently held in reset by the RST_N signal.

3. No clock is being supplied to the device.

4. The clock frequency supplied to the device is unsuitable for the selected PLL multiplier. The PLL multiplier is set using the MODE pins and should be configured so that the XCore boots up at or below its maximum frequency. Further details on the MODE pins can be found in the relevant device datasheet.

5. The VDD Core supply is outside of tolerance (1.0V +/-10%).

6. The VDD PLL supply is outside of tolerance (1.0V +/-10%) or not present. This will mean that the PLL is not locked and hence the XCore will be kept in reset. On an XS1-G series device the SS_PLL_LOCK output signal can be used to drive an active-high LED when the PLL has locked successfully.

7. The power supplies have not been correctly sequenced. The VDDIO (and OTP_VDDIO if present) supply must be within specification (3.0V-3.6V) before the VDD Core supply is turned on. Specifically, the VDDIO supplies should be within specification before VDD core reaches 0.4V.

8. The device, especially the ground paddle on the L1/L2 devices, has not been correctly soldered to the board. This can either be in the form of not connected solder joints or shorted solder joints to other pins, ground or power.

USB 相关知识

lib xua

组件	描述
Endpoint 0	提供Endpoint 0的逻辑，处理设备的枚举和控制，包括DFU相关请求。
Endpoint buffer	缓冲端点数据包的传输，用于主机和设备之间的音频数据包交换。还可以处理音量控制处理。请注意，目前使用了两个核心。
AudioHub	处理通过I2S进行的音频输入/输出，并管理与其他数字音频输入/输出组件之间的音频数据。

此外，还需要低级别的USB I/O，该功能由外部依赖项lib_xud提供。

组件	描述
XMOS USB Device Driver (XUD)	处理低级别的USB I/O

lib xua 可选组件

组件	描述
Mixer	允许对输入和输出通道进行数字混音。也可以处理音量控制，而不使用解耦器。
Clockgen	用于驱动外部频率发生器（PLL），管理内部时钟和来自数字输入的外部时钟之间的切换。
MIDI	通过串行UART接口进行MIDI输出和输入。

组件	描述
S/PDIF Transmitter	输出S/PDIF数字音频接口的样本。
S/PDIF Receiver	输入S/PDIF数字音频接口的样本（需要clockgen组件）。
ADAT Receiver	输入ADAT数字音频接口的样本（需要clockgen组件）。
PDM Microphones	从麦克风接收PDM数据，并执行PDM到PCM转换。